Renesas R8C series User Manual

R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface
Rev.1.30 Dec 08, 2006 Page 196 of 315
REJ09B0252-0130
Figure 16.20 Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Reception (4-Wire Bus Communication Mode)
SSCK
b0SSI
• CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops)
b7
SCS
(output)
SSCK
• CPHS bit = 1 (data download at odd edges) and CPOS bit = 0 (“H” when clock stops)
CPHS and CPOS: Bit in SSMR register
1 frame
RDRF bit in
SSSR register
0
1
RSSTP bit in
SSCRH register
0
1
Dummy read in
SSRDR register
Processing
by program
1 frame
High-impedance
b0b7
High-impedance
SCS
(output)
b7 b0
Data read in SSRDR
register
RXI interrupt request
is generated
RXI interrupt request
is generated
Data read in SSRDR
register
RXI interrupt request
is generated
b0b7b0b7
b7
b0SSI
1 frame
RDRF bit in
SSSR register
0
1
RSSTP bit in
SSCRH register
0
1
Dummy read in
SSRDR register
Processing
by program
1 frame
Data read in SSRDR
register
RXI interrupt request
is generated
RXI interrupt request
is generated
RXI interrupt request
is generated
Set RSSTP
bit to 1
Data read in SSRDR
register
Set RSSTP
bit to 1

Renesas R8C series Specifications

General

Brand	Renesas
Model	R8C series
Category	Computer Hardware
Language	English