R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface
Rev.1.30 Dec 08, 2006 Page 213 of 315
REJ09B0252-0130
Figure 16.33 Operating Timing in Master Transmit Mode (I
2
C bus Interface Mode) (1)
Figure 16.34 Operating Timing in Master Transmit Mode (I
2
C bus Interface Mode) (2)
SDA
(master output)
SCL
(master output)
12
8967453
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
12
SDA
(slave output)
TDRE bit in
ICSR register
1
0
TEND bit in
ICSR register
1
0
ICDRT register
ICDRS register
R/W
Slave address
Address + R/W
Processing
by program
(2) Instruction of
start condition
generation
(3) Data write to ICDRT
register (1st byte)
A
(4) Data write to ICDRT
register (2nd byte)
(5) Data write to ICDRT
register (3rd byte)
Data 2
Address + R/W
Data 1
Data 1
SDA
(master output)
SCL
(master output)
12
8967453
b7
b6
b5
b4
b3
b2 b1 b0
SDA
(slave output)
TDRE bit in
ICSR register
1
0
TEND bit in
ICSR register
1
0
ICDRT register
ICDRS register
Data n
Processing
by program
(6) Generate stop condition and
set TEND bit to 0
(3) Data write to ICDRT
register
A/A
(7) Set to slave receive mode
9
A
Data n