Renesas R8C series User Manual

C - 2
REVISION HISTORY R8C/1A Group, R8C/1B Group Hardware Manual
1.00 Sep 09, 2005 33 Table 5.18 Unassigned Pin Handling, Figure 5.11 Unassigned Pin
Handling;
“Port P4_2, P4_6, P4_7”
→ “Port P4_6, P4_7”
“VREF”
→ “Port P4_2/VREF” revised
53 Table 9.2 Bus Cycles for Access Space of the R8C/1B Group added,
Table 9.3 Access Unit and Bus Operation;
“SFR”
→ “SFR, Data flash”,
“ROM/RAM”
→ “Program ROM, ROM, RAM” revised
62 10.2.1 Low-speed On-Chip Oscillator Clock;
“The application products ... to accommodate the frequency range.”
→
“The application products ... for the frequency change.” revised
10.2.2 High-Speed On-Chip Oscillator Clock;
“The high-speed on-chip oscillator frequency ... for details.” added
69 10.5.1 How to Use Oscillation Stop Detection Function;
“This function cannot ... is 2 MHz or below.”
→
“This function cannot be ... is below 2 MHz.” revised
70 Figure 10.9 Procedure of Switching Clock Source From Low-Speed On-
Chip Oscillator to Main Clock revised
71 10.6.2 Oscillation Stop Detection Function;
“Since the oscillation ...frequency is 2MHz or below, ...”
→
“Since the oscillation ...frequency is below 2MHz, ...” revised
10.6.4 High-Speed On-Ship Oscillator Clock added.
85 Figure 12.10 Judgement Circuit of Interrupts Priority Level;
NOTE2 deleted
104 Figure 14.1 Block Diagram of Timer X;
“Peripheral data bus”
→ “Data Bus” revised
117 14.1.6 Precautions on Timer X;
“When writing “1” (count starts) to ... writing “1” to the TXS bit.”
→
‘ “0” (count stops) can be read ... after the TXS bit is set to “1”.’ revised
118 Figure 14.11 Block Diagram of Timer Z;
“Peripheral Data Bus”
→ “Data Bus” revised
135 14.2.5 Precautions on Timer Z;
“When writing “1” (count starts) to ... writing “1” to the TZS bit.”
→
‘ “0” (count stops) can be read ... after the TZS bit is set to “1”.’ revised
149 Figure 15.3 U0TB to U1TB, U0RB to U1RB and U0BRG to U1BRG
Registers;
“UARTi Transmit Buffer Register (i=0 to 1)” and
“UARTi Receive Buffer
Register (i=0 to 1)” revised
159 Table 15.5 Registers to Be Used and Settings in UART Mode;
UiBRG: “
−” → “0 to 7” revised
164 Table 16.1 Mode Selection;
“RE and TE Bits in SSER Register” added
193 16.2.8.2 Selecting SSI Signal Pin added
Rev. Date
Description
Page Summary

Renesas R8C series Specifications

General

Brand	Renesas
Model	R8C series
Category	Computer Hardware
Language	English