Rohde & Schwarz ZVL series - Status:questionable:integrity

R&S ZVL Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
340
2
Failed Limit Check for Trace no. 16
This bit is set if any point on trace no. 16 fails the limit check.
Numbering of traces
The traces numbers 1 to 16 are assigned as follows:
 Traces assigned to channels with smaller channel numbers have smaller trace numbers.
 Within a channel, the order of traces reflects their creation time: The oldest trace has the smallest,
the newest trace has the largest trace number. This is equivalent to the order of traces in the
response string of the CALCulate<Ch>:PARameter:CATalog? query.
 The number of traces monitored cannot exceed 16. If a setup contains more traces, the newest
traces are not monitored.
STATus:QUEStionable:INTegrity...
The STATus:QUEStionable:INTegrity register monitors hardware failures of the analyzer. It can be
queried using the commands STATus:QUEStionable:INTegrity:CONDition? or
STATus:QUEStionable:INTegrity[:EVENt]? STATus:QUEStionable:INTegrity is also the summary
register of the lower-level STATus:QUEStionable:INTegrity:HARDware register.
Refer to the Error Messages section for a detailed description of hardware errors including possible
remedies.
The bits in the STATus:QUEStionable:INTegrity register are defined as follows:
Bit
No.
Meaning
2
HARDware Register summary
This bit is set if a bit is set in the STATus:QUEStionable:INTegrity:HARDware register and the
associated ENABle bit is set to 1.
The STATus:QUEStionable:INTegrity:HARDware register can be queried using the commands
STATus:QUEStionable:INTegrity:HARDware:CONDition? or
STATus:QUEStionable:INTegrity:HARDware[:EVENt]?
The bits in the STATus:QUEStionable:INTegrity:HARDware register are defined as follows:
Bit
No.
Meaning
0
Not used
1
ExtRef unlock
With external reference signal (System – External Reference active) or option ZVAB-B4 (oven quartz),
the reference oscillator is phase locked to a 10 MHz signal. This bit is set if this phase locked loop (PLL)
fails.
For external reference: check frequency and level of the supplied reference signal.
3
Receiver overload
This bit is set if the analyzer detects an excessive input level at one of the ports.
Reduce RF input level at the port. Check amplifiers in the external test setup.