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Schweitzer Engineering Laboratories SEL-321 - Pole-Discordance Logic

Schweitzer Engineering Laboratories SEL-321
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Date Code 20011026 Specifications 2-15
SEL-321/321-1 Instruction Manual
If setting ELOP = N1, then settings LOPD and 50M are not used and are hidden. If setting
ELOP = Y1 or Y2, then setting LOPD is not used and is hidden. Setting 50M is still visible
since it is used in stub protection logic.
Settings
Enable Loss-of-Potential ELOP N = Disable element blocking. Monitor LOP
with original logic.
Y = LOP blocks distance elements with original
logic. Overcurrent elements default forward
during LOP condition.
N1= Disable element blocking. Monitor LOP
with advanced logic.
Y1= LOP blocks distance elements and overcurrent
directional elements with advanced logic.
Y2= LOP blocks distance elements with advanced
logic. Overcurrent elements default forward
during LOP condition.
LOP Time Delay LOPD Sets time delay before LOP can assert following the
loss of one or two potential fuses.
Medium-Set Phase O/C Pickup 50M Single-phase overcurrent threshold for blocking
LOP during faults, and for use in stub protection
logic.
Neg.-Seq. (V2) O/V Pickup 59QL Sets V2 threshold for detecting one or two blown
fuses.
Pos.-Seq. (V1) O/V Pickup 59PL Sets V1 threshold for detecting three blown fuses.
Outputs
LOP indication LOP Always available even if ELOP = N or N1. Does
not block distance elements.
Internal LOP block ILOP Enabled by ELOP = Y, Y1, or Y2. Blocks distance
elements.
Supporting Drawings: Figure 2.22 and Figure 2.38.
Pole-Discordance Logic
This logic can be used to alarm or trip. The logic checks the 52A inputs from either one or two
breakers. The timer, SPPDD, cycles after any single-pole trip signal drops out. If all three 52A
inputs from a breaker disagree, the appropriate pole-discordance output variable (PD1 or PD2)
immediately asserts.
Timer Setting
Single-Pole Trip
Phase-Discordance Delay SPPDD Sets time delay for checking the 52A input statuses
following the dropout of a single-pole trip signal.
Outputs
Pole Discordance 1 PD1 Breaker 1 pole discordance.
Pole Discordance 2 PD2 Breaker 2 pole discordance.
Supporting Drawing: Figure 2.39.

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