Testing cycle time monitoring
(During START-UP, without time slice)
With this function, the cycle time monitoring is checked during the
start-up phase. The cycle monitoring time is set to the minimum value
(20 ms) and then a program loop started until the cycle error occurs.
Testing the address lines
(Cyclically in RUN mode, with time slice)
In this test, wire breaks and short circuits on the address lines are
detected by writing test patterns via the lines, reading them back and
comparing them.
Testing the system program
code
(Cyclically in the RUN mode, with time slice)
In the operating code test, the content of the CPU operating system in
the internal RAM is checked (test area D 0000H to E 7FFDH).
The test is made by adding the content of the test area and then
comparing this with the checksum in the EPROM.
Testing the block code of
STEP 5 logic blocks
(Cyclically in the RUN mode, with time slice)
The checksum of each valid STEP 5 logic block is checked.
If a memory card is inserted, the checksum of the logic blocks of the
CPU 948 is created following an OVERALL RESET and after
copying the memory card contents to the internal user memory. Logic
blocks added at a later point in time are also checked.
Note
In the code test of the STEP 5 blocks, an error is detected if one or
more logic blocks were modified dynamically.
It is possible to modify blocks with the PG. If this is the case, the
checksum is created by the system program of the CPU 948.
Self-Test
CPU 948 Programming Guide
5 - 36 C79000-G8576-C848-04
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