[logikdia-ip-stufe-amz-iec-wlk-310702, 1, en_GB]
Figure 2-17
Logic diagram of the Ι
P
stage (inverse time overcurrent protection), for example IEC character-
istics
1) The output indications associated with the pickup signals can be found in Table 2-3
2) The output indications associated with the trip signals can be found in Table 2-4
End fault stage
A further overcurrent stage is the stub protection. It can, however, also be used as a normal additional definite
time overcurrent stage, as it functions independently of the other stages.
A stub fault is a short-circuit located between the current transformer set and the line isolator. It is of partic-
ular importance with the 1
1
/
2
circuit breaker arrangements.
Functions
2.3 Overcurrent protection (optional)
SIPROTEC 4, 7VK61, Manual 71
C53000-G1176-C159-5, Edition 05.2018
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