[logikdiagramm-i-vg-stufe-wlk-310702, 1, en_GB]
Figure 2-16
Logic diagram of the Ι stage
1) The output indications associated with the pickup signals can be found in Table 2-3
2) The output indications associated with the trip signals can be found in Table 2-4
Definite time overcurrent stage Ι>
The logic of the overcurrent stage Ι is the same as that of the Ι stages. In all references Iph>> must merely be
replaced by Iph> or 3I0>> PICKUP by 3I0>. In all other respects Figure 2-16 applies.
Inverse time overcurrent stage Ι
P
The logic of the inverse overcurrent stage also operates chiefly in the same way as the remaining stages.
However, the time delay is calculated here based on the type of the set characteristic, the intensity of the
current and a time multiplier (following figure). A pre-selection of the available characteristics was already
carried out during the configuration of the protection functions. Furthermore, an additional constant time
delay T Ip Add (address 2646) or T 3I0p Add (address 2656) may be selected, which is added to the
inverse time. The possible characteristics are shown in the Technical Data.
The following figure shows the logic diagram. The setting addresses of the IEC characteristic curves are shown
by way of example. In the setting notes, the different setting addresses are described in detail.
Functions
2.3 Overcurrent protection (optional)
70 SIPROTEC 4, 7VK61, Manual
C53000-G1176-C159-5, Edition 05.2018
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