Functions
6-134 7SA522 Manual
C53000-G1176-C119-2
I>> Anr L1
Figure 6-77 Logic diagram of the I>>–stage
Definite Time Over-
current Stage I>
The logic of the overcurrent stage I> is the same as that of the I>>–stage. All referenc-
es to Iph>> must simply be replaced by ,SK! and 3I0>> by ,!. In all other respects
Figure 6-77 applies.
Inverse Time Over-
current Stage I
p
The logic of the inverse overcurrent stage also in principal functions the same as the
remaining stages. The time delay in this case however results from the nature of the
set characteristic (parameter /2*&XUYH), the magnitude of the current and the time
multiplier (Figure 6-78). A pre-selection of the available characteristics was already
done during the configuration of the protection functions. Furthermore, an additional
constant time delay 7,S$GG (address 2646) may be selected, which are added to
the current dependant time derived from the IDMT characteristic. The available char-
acteristics are shown in the technical data, Section 10.9.
Figure 6-78 shows the logic diagram. The setting parameter addresses of the IEC
characteristics are shown by way of an example. In the setting information (Sub-sec-
tion 6.9.2) the different setting addresses are elaborated upon.
I>> Pickup L3
I>> Pickup L2
I>> Trip L3
I>> Trip L2
I
L3
I
L2
I
L1
Iph>
&
7,SK!!
T0
&
≥1
Yes
No
,!!627)
Yes
No
,!!7HOHS%,
Switch onto
fault
≥1
further
stages
L3
L2
L1
3I0>>
&
T0
&
≥1
E
7,!!
,!!
I
E
I>> Pickup L1
I>> Trip L1
I>> Trip E
I>> Pickup E
T0
7104
>BLOCK O/C I>>
7110
>O/C InstTRIP
627)7LPH'(/$<
,SK!!
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