ST ST7 - Page 64

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4 - Architecture of the ST7 core
04-core
Accumulator
X index register
Y index register
Stack pointer
Program counter
Condition code register
Arithmetic
and logic
unit
CPU Control
Core
Reset
CPU Clock
Interrupt
requests from
peripherals
Data Memory
from 0000h to 017Fh:
Peripheral registers
User RAM
Stack RAM
Program Memory
from E000h to FFFFh
user ROM
Interrupt & reset vectors
Address bus
Data bus
(16 lines wide)
( 8 lines wide)
(16 lines wide)
Page 0
( 8 lines wide)
The core and the addressing space of the ST72251