4.5.1 Power Sequencing
Figure 4-4 shows the power up sequence of the all Power supplies present on the processor card. Note
processor specific power supplies are provided from the Dual PMICs, and its specific power sequence is to
support the processor sequence requirements. This sequence is documented in the device-specific processor's
data manual. Figure 4-4 illustrates the support of all the other system supplies.
J7ES_CP Board Power Sequencing
Power
input
(from
jack)
SW
CP Board Power Sequencing
IN
Over voltage
protection
circuit
VMAIN
EN
IN
OUT
VINPUT
DUAL BUCK
REG
5V, 10A
3.3V, 10A
(LM5140)
Type C PD
CTRLR
5V, 3.5A
(TPS25830)
BUCK REG
3.3V, 20A
(LM5141
-Q1)
BUCK
-BOOST REG
12V,10A
(LM5175)
LDO
3.3V/1.8V
TLV7103318
LOAD SW
TPS1H100A
LOAD SW
TPD3S014
(USB2.0 TYPE A
CONN)
LDO
3V3,1.5A
(TPS74801)
LDO
2V5,1.5A
(TPS74801)
LDO
1V0,1.5A
(TPS74801)
STEP UP
REG
TPS61240
IN
IN
EN
VSYS_IO_3V3
EN2
IN
EN1
PG
VOUT 1
VOUT 2
PG
IN
EN
PG 1
IN
IN
EN
EN1
VIN
LDO
3V3,1.5A
(TPS74801)
IN
EN
PG
LDO
1V1,1.5A
(TPS74801)
VSYS_5V0
V3V3
VIN
EN
EN
EN
VIN
EN
VSYS_MCUIO_3V3
IN
EN
LOAD SW
TPD3S014
(USB 3.0uAB)
IN
EN
IN
VS
VCC_12V0
VOUT
Reverse polarity
protection circuit
PG 2
LOAD SW
TPS1H100A
IN
VS
VIN
USBC_PWR_EN
USB1_DN1_PE*
USB1_DN2_PE*
LOAD SW
TPD3S014
(USB2.0 TYPE A
CONN)
IN
EN
DP1_PWR_SW_EN*
DP0_PWR_SW_EN*
EN2
CSI_VIO_SEL*
USB2_DRVVBUS*
VSYS_IO_3V3
PWR_SW_CNTL_DSI0*
R
UB926_PWR_SW_CNTRL*
TA_PORZ#
PMIC_PORz
PCIe1_PORz
PCIe0_PORz
PORz
R
VSYS_IO_3V3
EN
*
Pull down with resistor & regulators/switch OFF by default
VBUS_5V_CONN1
VBUS_5V_CONN2
V3V3_DP0
V3V3_DP1
VCC_CSI_IO
VBUS_USB2
VCC_1V1
VDD_2V5
VDD_1V0
VSYS_MCU_5V0
VCC_12V0_FPD
VCC_12V_DSI0
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
EXP_3V3
OUT
SOM/PMIC
R
R
VSYS_3V3
VSYS_3V3_SOM
SYS_MCU_EN
VBUS_USBC_CONN
OUT
LOAD SW
TPS22918DBVR
VIN
ON
GPIO_uSD_PWR_EN
R
VSYS_IO_3V3
VDD_MMC1
OUT
LM5140_PG1
LM5140_PG2
LM5141_PG
LM5175_PG
R
R
LM5140_PG1
LM5175_PG
R
LM5141_PG
Voltage Monitor
TPS3711DDCR
RESET
SENSE
VIN_MON_PORZ
VINPUT
Voltage Monitor
TPS3808G33DBVR
RESET
SENSE
VSYS_3V3
SYS_PWR_PG
PMIC_MCU_PORz
MCU_PORz
R
LM5140_PG2
R
LM5141_PG
SoC Power on Reset Logic
Figure 4-4. Power ON Sequencing
J721E EVM Hardware Architecture www.ti.com
32 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022
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