4.23 Apple Authentication Header
The common processor board has a provision to support Apple authentication interface. In the J721E EVM, the
Apple authentication board can be interfaced with J721E SoC in two options: one is module interface and the
other is device interface.
J721ESOM
PG-USON-8-1
Footprint
I2C0_SCL
I2C0_SDA
APPLE_AUTH_RSTz
From GPIO
Expander
3.3 V
NC
NC
NC
NC
NC
3.3 V
1 2
3
5 6
7 8
9 10
4
Option ± 1
Option ± 2
DNI
Figure 4-42. Apple Authentication Block Diagram
Module Interface:
Common Processor board have a 2.54 mm Dual row 10 Pin Receptacle Mfr. Part# 2214BR‐10G.
I2C0 Port of J721E SoC and Reset from GPIO Expander is terminated to this connector. 3.3 V supply is provided
to the connector J9.
Table 4-27 lists detailed signal and pin descriptions.
Table 4-27. APPLE AUTH Header J9 Pinout
Pin No Signal Description
1 I2C0_SCL I2C slave interface, clock connection
3 I2C0_SDA I2C slave interface, data connection
8 APPLE_AUTH_RSTz Reset, Active low
5 VSYS_IO_3V3 Power 3.3 V
2 DGND Ground
4,6,7,9
,10
NC Not Connected
J721E EVM Hardware Architecture www.ti.com
72 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022
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