4.25.2.2 Optional Clock
Optionally, the reference clock can be supplied by the SERDES clock generator Mfr. Part Number#
CDCI6214RGET, located on Quad port Ethernet Expansion Board, which can be configured by I2C0 of the
J721E SOC. The I2C address of this clock generator is 0x77 and this address conflicts with CDCI Chip on
Common processor Board. An I2C switch on Quad port Ethernet Expansion Board is used to remove the
address conflict by either connecting any one of the clock generators.
Figure 4-44. CDCI I2C Isolation Circuit
Set the CDCI_I2C_SEL I/O EXP bit high to connect the I2C bus to the CDCI for programming on the Quad Port
Ethernet Expansion Board. During this time, the CDCI device U17 on the Common Processor board should be in
reset mode.
J721E EVM Hardware Architecture www.ti.com
78 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022
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