Texas Instruments J721E User Manual

4.7 Clock
Figure 4-8 shows the J721E EVM clock architecture.
J7E21E SOC
Crystal
32.768kHz
WKUP_LFOSC_XI
WKUP_LFOSC_XOUT
Crystal
19.2MHz
Crystal
22.5792MHz
SERDES0
SERDES1
SERDES2
SERDES4
SOM
WKUP_OSCO_IN
OSC0_IN
WKUP_OSC0_OUT
OSC0_OUT
100MHz P/N
From CP board Clock GEN
Clock
Generator
CDCI6214
R
R
R
R
R
R
R R
PCIe Slot
(x1L)
100MHz P/N
PCIe Slot
(x2L)
100MHz P/N
Clock
Generator
CDCI6214
R
R
R
R
R R
PCIe Slot
(M.2)
100MHz P/N
ENET
EXPANSION
125MHz P/N
100MHz P/N
100MHz P/N
100MHz P/N
Clock
Generator
CDCEL937
-
Q1
1.8V
25MHz
XTAL
MCU RGMII
PHY
R
R
25MHz
REF
XTAL
25MHz
REF
XTAL
25MHz
REF
XTAL
22.5792MHz
GESI/INFO
EXPANSION
(RGMII)
USB
HUB
TUSB4041
DSI TO
FPD
BRIDGE
24MHz
XTAL
R
R
XTAL
R
R
25MHz
24MHz
25MHz
CSI2
EXPANSION
25MHz
CP Board
LVL
TXLR
GESI/INFO
EXPANSION
(SPARE)
25MHz
100MHz P/N
SERDES3
RTC
Module
32.768KHz
XTAL
R
R
From CP board RTC Module
Figure 4-8. EVM Clock Architecture
EVM supports multiple Crystals and Clock generator to provide the reference clock input to the SoC and EVM
peripherals.
www.ti.com J721E EVM Hardware Architecture
SPRUIS4D – MAY 2020 – REVISED MARCH 2022
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) 39
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Texas Instruments J721E Specifications

General

Brand	Texas Instruments
Model	J721E
Category	Motherboard
Language	English