5 Hardware Design Files
5.1 Schematics
330pF
C14
330pF
C15
10uF
C16
10uF
C17
GND GND
730_LDO_3V3
730_LDO_1V5
0.1uF
C1
GND
0.1uF
C8
10uF
C9
GND GND
730_VIN_3V3
730_CC1
730_CC2
730_CC2
730_CC1
730_PPHV
1 2
3 4
5 6
J1
P E C 0 3 DAAN
Place capacitors close to chip 0.01uF
C2
0.01uF
C3
0.01uF
C4
0.01uF
C5
GND
L1
IN
4
IN
5
GND
1
GND
2
IN
6
GND
3
PAD
7
TVS2200DRVR
U2
730_VBUS
730_VBUS730_VBUS_IN
VBAT
VSYS
GND GND GND GND
21
Blue
D4
10.0k
R14
GND
VSYS LED Indicator
1uF
C7
GND
SH-J1
SH-J2
SELECTOR BATTERY VS TYPE-C
VSYS
VSYS
730_PPHV
TP4
TP5
Test Points
TP8
GND
ADCINx CONFIG
Decoded ADCINx
3
7
ADCIN1:
ADCIN2:
21
Blue
D1
10.0k
R9
GND
Type C LED Indicator
10.0k
R13
GND
21
Blue
D3
VBAT
VBAT LED Indicator
10uF
C10
10uF
C11
10uF
C12
10uF
C13
GND
GND GND GND
P_ADCIN1 P_ADCIN2
730_LDO_3V3
200k
R4
200k
R1
GND
Configuration
1uF
C6
GND
GND
730_DRAIN
2.20k
R11
2.20k
R10
730_LDO_3V3
GND
P_ADCIN1
P_ADCIN2
ADCIN3:
ADCIN4:
Minimu m Vo ltage Config ura tion: 15V
Maximu m Vo ltage Config ura tion 20V
3
3
Ope ra ting Curre nt:
Maximu m Current:
Minimu m Powe r Re quired:
3A
5A
45W
P_ADCIN3
P_ADCIN4
P_ADCIN3 P_ADCIN4
51.0k
R6
51.0k
R7
51.0k
R8
200k
R3
200k
R5
100k
R105
GND
100k
R94
3
1
2
Q4
Red
21
D8
15 0060RS 75000
10.0k
R95
GND
100k
R96
730_LDO_3V3
100k
R12
100k
R23
100k
R75
100k
R56
10.0k
R2
LDO_3V3
1
VIN_3V3
38
ADCIN1
2
ADCIN2
3
ADCIN3
5
ADCIN4
7
I2Ct_SCL
9
I2Ct_SDA
8
PLUG_EVENT
37
PLUG_FLIP
13
DRAIN
15
DRAIN
30
FAULT_IN
18
Reserved
36
VBUS
32
VBUS_IN
23
Reserved
26
Reserved
27
CAP_MIS
6
DBG_ACC
10
LDO_1V5
4
PPHV
20
SINK_EN
19
DRAIN_PAD
40
CC1
28
CC2
29
GND
11
GND
12
GND
14
GND
16
GND
17
GND
31
GND
34
GND_PAD
39
PPHV
21
PPHV
22
VBUS
33
GND
35
VBUS_IN
24
VBUS_IN
25
TPS25730DREFR
U1
Figure 5-1. TPS25730 Power Input Schematic
www.ti.com Hardware Design Files
SLVUCP9A – NOVEMBER 2023 – REVISED MARCH 2024
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TPS25751 Evaluation Module 33
Copyright © 2024 Texas Instruments Incorporated
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