Xerox 550 User Manual

8. Real addressing is allowed in master mode and in slave
mode, and is specified when bit positions 9 and 61 of
the PSWs both contain zero.
VIRTUAL ADDRESSING
Virtua
I addressing uses the memory map to determine the
actual address to be associated with a particular reference
address of each instruction. Virtual addressing differs from
real addressing in that there is normally no exact relation-
ship between the effective virtual address and the actual
address. These are the characteristics of virtual addressing:
1. Each reference address is a 17-bit address.
2. The reference address may be direct or indirect, with
or without postindexing.
3. Displacements associated with indexing are automati-
cally aligned, as required, using the full 32-bit
contents of the index register. The final result is
truncated to the left of the high-order bit of the
original 17-bit reference address, and the effective
virtual address is a 16-bit doubleword address, 17-bit
word address, 18-bit halfword address, or a 19-bit byte
address.
4. Virtua I memory access protection is always invoked.
If the access protection code is invalid, the instruction
aborts and traps to location X 140
1
•
(See "Trap System",
later in this chapter.)
5. Memory mapping translates the 8 most significant bits
of the effective virtual address (the page portion) into
an l1-b i t page address. Th is page address is concate-
nated with the 9 least significant bits of the reference
address. The resultant 20-bit word address is the actual
address used to access memory. This feature permits
anyone user at any given time to have a virtual mem-
ory
of as many as 128K words (256 pages) located
throughout real (actual) memory comprising as many
as 256K words (512
pages). Although virtual memory
may
be physically fragmented, it is logically contiguous.
Note that Sigma 6/1 programs may run on this computer
system
without requiring change to the mapping struc-
ture. The memory map is loaded with 8-bit page ad-
dresses (the 3 high-order bits of the ll-bit real page
address are reset to zeros). The most significant 8 bits
of the effective virtual address are then translated into
the designated 8-bit page address.
6. The rnemory write-protection featl.!re !5 !n'loked for the
actual address in real memory.
7. Virtual addressing may be used in all modes (master,
master-protected, and slave) and is specified when
bit 9 of the PSWs contains a one.
20 Main Memory
ADDRESS MODIFICATION EXAMPLE: INDEXING
(REAL AND VIRTUAL ADDRESSING)
Figure 6 shows how
the indexing operation takes place dur-
ing real and virtual addressing operations. The instruction
is brought from memory and loaded into a 34-bit instruction
register that initially contains zeros in the two low-order
bit positions (32 and 33). The displacement value from the
index register is then aligned with the instruction register
(as an integer) according to the address type of the instruc-
tion; that is, if it is a byte operation, the low-order bit of
the displacement is aligned with the least significant bit of
the 34-bit instruction register (bit position 34). The dis-
placement is then shifted one bit to the left of this position
for a halfword
operation, two bits to the left for a word
operation, and three bits to the left for a doubleword oper-
ation. An addition process then takes place to develop a
19-bit address, referred to as the effective address of the
instruction. High-order bits of the 32-bit displacement are
ignored in the devdopment of this effective address (i .e.,
the 15 high-order bits are ignored for word operations, the
25 high-order bits are ignored for shift operations, and the
16 high-order bits are ignored for doubleword operations).
The displacement value, however, can cause the effective
address to be less than the initial reference address (within
the instruction) if the displacement value contains a suffi-
cient number of high-order lis (i .e., if the displacement
value is a negative integer in two1s complement form).
The
effective virtual address of an instruction is always a
19-bit byte address value. This value, however, is auto-
matically adjusted to the information boundary conventions.
Thus, for halfword operations the low-order bit of the effec-
tive halfword address is zero; for word operations the two
low-order bits of the effective word address are zeros; and
for doubleword operations the three low-order bits of the
effective doubleword address are zeros.
In a byte operation with no indexing, the effective byte
is the first byte (byte 0 in bit positions 0-7) of a word lo-
cation; in a halfword operation with no indexing, the ef-
fective halfword is the first halfword (halfword 0 in bit
positions 0-15) of a word location. A doubleword opera-
tion always involves a word at an even numbered address
and the word at the next sequential (which is odd numbered)
word address. Thus,
if an odd numbered word location
is specified for a doubleword operation, the low-order bit of
the effective address field (bit position 31) is automatically
forced to zero. This means that in a doubleword operation
an odd numbered word (reference) address designates the
same doubleword as the next lower even numbered word
address.
In the real addressing mode, the 19-bit effective virtual
address is concatenated with 3 leading zeros to form a
22-b it actua I address. In the virtua I addressi ng mode,
the 8 most significant bits of the 19-bit virtual address
are mapped (using the memory map) into the 11-bit actual
page address, thus forming a 22-bit actual address.

Xerox 550 Specifications

General

Monthly Duty Cycle	Up to 300, 000 pages
Connectivity	Ethernet, USB
Print Speed (Color)	Up to 50 ppm
Duplex Printing	Standard
Printer Type	Laser
Supported Operating Systems	Windows, macOS, Linux
Paper Size	A4, Legal, Letter