Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 107
UG482 (v1.9) December 19, 2016
TX Fabric Clock Output Control
Ports and Attributes
Table 3-22 defines the ports required for TX polarity control.
Using TX Polarity Control
TXPOLARITY can be tied High if the polarity of TXP and TXN needs to be reversed.
TX Fabric Clock Output Control
Functional Description
The TX Clock Divider Control block has two main components: serial clock divider control and
parallel clock divider and selector control. The clock divider and selector details are illustrated in
Figure 3-20.
Table 3-22: TX Polarity Control Ports
Port Dir Clock Domain Description
TXPOLARITY In TXUSRCLK2 The TXPOLARITY port is used to invert the polarity
of outgoing data.
0: Not inverted. TXP is positive, and TXN is
negative.
1: Inverted. TXP is negative, and TXN is positive.
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English