Xilinx 7 Series User Manual

196 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
Setting Clock Correction Sequences
The clock correction sequences are programmed using the CLK_COR_SEQ_1_* attributes and
CLK_COR_SEQ_LEN. Each CLK_COR_SEQ_1_* attribute corresponds to one subsequence in
clock correction sequence 1. CLK_COR_SEQ_LEN is used to set the number of subsequences to be
matched. If the 40-bit or 20-bit internal datapaths are used, the clock correction circuit matches all
10 bits of each subsequence. If the 16-bit or 32-bit internal datapaths are used, only the right-most
eight bits of each subsequence are used.
A second, alternate clock correction sequence can be activated by setting CLK_COR_SEQ_2_USE
to TRUE. The first and second sequences share length settings, but use different subsequence values
for matching. Set the CLK_COR_SEQ_2_* attributes to define the subsequence values for the
second sequence.
When using 8B/10B decoding (RX8B10BEN is High), CBCC_DATA_SOURCE_SEL is set to
DECODED to search the output of the 8B/10B decoder for sequence matches instead of
non-decoded data. This allows the circuit to look for 8-bit values with either positive or negative
disparity, and to distinguish K characters from regular characters (see TX 8B/10B Encoder, page 83
and RX 8B/10B Decoder, page 170 for details). Figure 4-45 shows how to set a clock correction
sequence byte when RX8B10BEN is High and CBCC_DATA_SOURCE_SEL is set to DECODED.
When CBCC_DATA_SOURCE_SEL is set to ENCODED, the sequence must exactly match
incoming raw data. When RX_DISPERR_SEQ_MATCH is set to FALSE,
CLK_COR_SEQ_x_y[9] is not used for matching.
Some protocols use clock correction sequences with don’t care subsequences. The clock correction
circuit can be programmed to recognize these sequences using CLK_COR_SEQ_1_ENABLE and
CLK_COR_SEQ_2_ENABLE. When the enable bit for a sequence is Low, that byte is considered
matched no matter what the value is. Figure 4-46 shows the mapping between the clock correction
sequences and the clock correction sequence enable bits.
X-Ref Target - Figure 4-45
Figure 4-45: Clock Correction Subsequence Settings with
CBCC_DATA_SOURCE_SEL = DECODED
UG482_c4_27_111011
CLK_COR_SEQ_x_y 9 8 7:0
8-bit Clock Correction Sequence
1 = Sequence is a K Character
0 = Sequence is a Regular Character
1 = Sequence Uses Inverted Disparity
0 = Sequence Uses Regular Disparity
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600

Summary

Chapter 1: Transceiver and Tool Overview

Overview and Features

Summary of GTP transceiver features and capabilities, including data rate and protocol support.

7 Series FPGAs Transceivers Wizard

Details on using the Wizard to generate GTP transceiver instantiation wrappers.

Simulation

Prerequisites and considerations for simulating GTP transceiver designs.

Implementation

Information on mapping GTP transceivers to device resources and creating UCF files.

Chapter 2: Shared Features

Reference Clock Input Structure

Description of the reference clock input buffer and its internal structure.

Reference Clock Selection and Distribution

Options for reference clock input, routing, and selection for GTP transceivers.

PLL

Details on the ring oscillator PLLs (PLL0 and PLL1) within the GTP Quad.

Reset and Initialization

Procedure for initializing the GTP transceiver after FPGA configuration.

Reset Modes

Explanation of sequential and single reset modes for GTP transceiver operation.

PLL Reset

Procedure for resetting the PLLs (PLL0 and PLL1) before use.

TX Initialization and Reset

Details on the TX reset state machine and its operation.

RX Initialization and Reset

Overview of RX initialization and reset processes, including sequential and single modes.

Power Down

Description of power-down modes for GTP transceiver channels and PLLs.

Loopback

Configuration and functionality of loopback modes for transceiver testing.

Dynamic Reconfiguration Port

Interface for dynamically changing parameters of GTPE2_CHANNEL and GTPE2_COMMON primitives.

Digital Monitor

Visibility into adaptation loops and convergence states for link optimization.

Chapter 3: Transmitter

TX Overview

Introduction to the GTP transceiver transmitter's functional blocks.

FPGA TX Interface

The FPGA's gateway to the TX datapath, including interface width and clocking.

TX 8B/10B Encoder

Functionality, bit/byte ordering, and K characters for 8B/10B encoding.

TX Gearbox

Support for 64B/66B and 64B/67B encoding for high-speed data protocols.

TX Buffer

Description of the TX buffer and phase alignment circuit for resolving clock domain differences.

TX Buffer Bypass

Advanced feature for adjusting phase difference and TX delay alignment.

TX Pattern Generator

Generation of PRBS and other test patterns for signal integrity testing.

TX Configurable Driver

Features of the TX driver, including voltage control, pre-emphasis, and termination.

TX Receiver Detect Support for PCI Express Designs

Feature for the transmitter to detect receiver presence on a link.

TX Out-of-Band Signaling

Support for OOB sequences in SATA/SAS and beaconing in PCI Express.

Chapter 4: Receiver

RX Overview

Introduction to the GTP transceiver receiver's functional blocks.

RX Analog Front End

Description of the RX analog front end buffer with configurable termination.

RX Out-of-Band Signaling

Support for OOB sequences in SATA/SAS and beaconing in PCI Express.

RX Equalizer

Power-efficient adaptive CTLE for compensating signal distortion.

RX CDR

Clock and data recovery circuit architecture and operation.

RX Fabric Clock Output Control

Control of serial and parallel clock dividers for the RX datapath.

RX Margin Analysis

Mechanism to measure and visualize receiver eye margin after equalization.

RX Polarity Control

Functionality to invert the polarity of incoming data.

RX Pattern Checker

Built-in PRBS checker for testing signal integrity.

RX Byte and Word Alignment

Process of aligning serial data to symbol boundaries for parallel data usage.

RX 8B/10B Decoder

Decoding of 8B/10B encoded data, including features and error handling.

RX Buffer Bypass

Advanced feature to bypass the RX elastic buffer for reduced latency.

RX Elastic Buffer

Functionality of the RX elastic buffer for resolving clock domain phase differences.

RX Clock Correction

Mechanism to bridge clock domain differences and prevent buffer overflow/underflow.

RX Channel Bonding

Feature to cancel skew between lanes by adjusting RX elastic buffer latency.

RX Gearbox

Support for 64B/66B and 64B/67B header and payload separation.

FPGA RX Interface

The FPGA's gateway to the RX datapath, including port widths and clocking.

Chapter 5: Board Design Guidelines

Overview

Introduction to implementing GTP transceiver designs on printed circuit boards.

Pin Description and Design Guidelines

Guidelines for routing GTP transceiver signals and managing SelectIO activity.

GTP Pin Descriptions

Detailed description of GTP Quad pins and their functions.

Termination Resistor Calibration Circuit

Description of the RCAL circuit for resistor calibration.

Analog Power Supply Pins

Discussion of MGTAVCC and MGTAVTT power planes and their organization.

Reference Clock

Selection criteria for reference clock sources and oscillators.

Power Supply and Filtering

Considerations for analog power supplies, regulators, and filtering.

PCB Design Checklist

A checklist for designing and reviewing GTP transceiver PCB schematics and layouts.

Appendix A: Placement Information by Package

CPG236 Package Placement Diagram

Placement diagram for the CPG236 package, showing GTP transceiver locations.

CSG325 Package Placement Diagram

Placement diagram for the CSG325 package, showing GTP transceiver locations.

CLG485 Package Placement Diagram

Placement diagram for the CLG485 package, showing GTP transceiver locations.

FGG484 Package Placement Diagram

Placement diagram for the FGG484 package, showing GTP transceiver locations.

FGG676 Package Placement Diagram

Placement diagram for the FGG676 package, showing GTP transceiver locations.

FBG484 Package Placement Diagram

Placement diagram for the FBG484 package, showing GTP transceiver locations.

SBG484 Package Placement Diagram

Placement diagram for the SBG484 package, showing GTP transceiver locations.

FFG1156 Package Placement Diagram

Placement diagram for the FFG1156 package, showing GTP transceiver locations.

Appendix B: Placement Information by Device

Appendix C: 8B/10B Valid Characters

Appendix D: DRP Address Map of the GTP Transceiver