Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 23
UG482 (v1.9) December 19, 2016
Chapter 2
Shared Features
Reference Clock Input Structure
Functional Description
The reference clock input structure is illustrated in Figure 2-1. The input is terminated internally
with 50Ω on each leg to 4/5 MGTAVCC. The reference clock is instantiated in software with the
IBUFDS_GTE2 software primitive. The ports and attributes controlling the reference clock input
are tied to the IBUFDS_GTE2 software primitive.
Figure 2-1 shows the internal structure of the reference clock input buffer.
X-Ref Target - Figure 2-1
Figure 2-1: Reference Clock Input Structure
MGTAVCC = 1.0V
MGTREFCLK[0/1]P
MGTREFCLK[0/1]N
MGTAVSS
I
CLKRCV_TRST
CEB
O
ODIV2
REFCLK_CTRL[1:0]
1'b0
/2
TO HROW
Reserved
TO GTREFCLK0/1 of
GTPE2_COMMON
Nominal 50
4/5
MGTAVCC
CLKCM_CFG
IB
+
-
2'b00
2'b01
2'b10
2'b11
UG482_c2_01_112811
Nominal 50
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600