Xilinx 7 Series User Manual

34 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 2: Shared Features
Figure 2-8 shows two GTP Quads, each utilizing their own dedicated differential reference clock
inputs as well as the dedicated differential reference clock inputs of their neighboring GTP Quad.
Such a scenario is only possible in the largest Artix-7 device (XC7A200T-FFG1156) that contains
east and west GTP Quads adjacent to each other. The user is responsible for properly connecting the
output of the IBUFDS_GTE2 to the appropriate GTREFCLK[0/1], GTWESTREFCLK[0/1], and
GTEASTREFCLK[0/1] input ports on the GTPE2_COMMON primitive.
For multi-rate designs that require the reference clock to be changed in real time, the
PLL0REFCLKSEL and PLL1REFCLKSEL ports are used to dynamically select the reference clock
source. When the selection has been made, the user design is responsible for resetting the PLL via
PLL0RESET or PLL1RESET.
PLL
Functional Description
The GTP Quad contains two ring oscillator PLLs (PLL0 and PLL1). The internal clocking
architecture is shown in Figure 2-9. When the TX and RX datapaths operate in the same line rate
range, PLL0 or PLL1 can be shared between the TX and RX datapaths. The TX and RX clock
dividers can individually select the clock from PLL0 or PLL1 to allow the TX and RX datapaths to
operate at asynchronous frequencies using different reference clock inputs.
X-Ref Target - Figure 2-8
Figure 2-8: Two GTP Quads using Multiple Reference Clocks from Different Quads
UG482_c2_08_110811
GTPE2_
CHANNEL
GTREFCLK0 GTREFCLK1 GTWESTREFCLK0 GTWESTREFCLK1
GTPE2_COMMON
GTPE2_
CHANNEL
GTPE2_
CHANNEL
GTPE2_
CHANNEL
GTP Quad
IBUFDS_
GTE2
IBUFDS_
GTE2
GTPE2_
CHANNEL
GTREFCLK0 GTREFCLK1 GTEASTREFCLK0 GTEASTREFCLK1
GTPE2_COMMON
GTPE2_
CHANNEL
GTPE2_
CHANNEL
GTPE2_
CHANNEL
GTP Quad
IBUFDS_
GTE2
IBUFDS_
GTE2
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Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English