Xilinx 7 Series User Manual

114 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 3: Transmitter
TX Configurable Driver
Functional Description
The GTP transceiver TX driver is a high-speed current-mode differential output buffer. To
maximize signal integrity, it includes these features:
• Differential voltage control
• Pre-cursor and post-cursor transmit pre-emphasis
• Calibrated termination resistors
Ports and Attributes
Table 3-28 defines the TX configurable driver ports.
X-Ref Target - Figure 3-21
Figure 3-21: TX Configurable Driver Block Diagram
Pre-Driver
PISO
TX Serial Clock=
Data Rate/2
TXDIFFCTRL[3:0]
TXPRECURSOR[4:0]
MGTAVTT
TXP
TXN
TXPOSTCURSOR[4:0]
Pre-Emphasis
Pad Driver
Main
Pad Driver
Post-Emphasis
Pad Driver
Pre-Driver
Pre-Driver
UG482_c3_20_110911
5050
Table 3-28: TX Configurable Driver Ports
Port Dir Clock Domain Description
TXBUFDIFFCTRL[2:0] In Async Pre-driver Swing Control. The default is 3’b100 (nominal value).
Do not modify this value.
TXDEEMPH In TXUSRCLK2 TX de-emphasis control for PCI Express PIPE 2.0 interface. This signal is
mapped internally to TXPOSTCURSOR via attributes.
0: 6.0 dB de-emphasis (TX_DEEMPH_0[4:0] attribute)
1: 3.5 dB de-emphasis (TX_DEEMPH_1[4:0] attribute)
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600