7 Series FPGAs GTP Transceivers User Guide www.xilinx.com UG482 (v1.9) December 19, 2016
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Revision History
The following table shows the revision history for this document.
Date Version Revision
01/03/2012 1.0 Initial Xilinx release.
02/21/2012 1.1 Changed “N” factor to “N1” and “N2”factors in Figure 2-10, Equation 2-1, and Table 2-7.
Revised Figure A-4, Figure A-6, Table B-1, Table D-1, and Table D-2.
01/01/2012 1.1.1 Made typographical edits.
09/06/2012 1.2 Updated the second, third, and fourth paragraphs under Overview and Features in Chapter 1.
Updated description of PLL0_FBDIV/PLL1_FBDIV and added PLL0_FBDIV_45/
PLL0_FBDIV_45 attributes to Table 2-9. Added Reset and Initialization and Power Down in
Chapter 2. Updated Note 1 relevant to Figure 3-2 through Figure 3-5. Updated descriptions of
TXSTARTSEQ and GEARBOX_MODE attributes in Table 3-9. Updated controller port clock
domains and descriptions in Table 3-26. Updated TXPI_SYNFREQ_PPM[2:0] and
TXPI_GREY_SEL attribute descriptions in Table 3-27. Updated first introductory paragraph
under TX Gearbox Operating Modes in Chapter 3. Deleted Internal Sequence Counter Operating
Mode section in Chapter 3, Transmitter. Added USE_PCS_CLK_PHASE_SEL and
ES_CLK_PHASE_SE attributes to Table 4-20. Added second and third paragraphs under
Alignment Status Signals in Chapter 4. Added last sentence to description of
RXBYTEISALIGNED port in Table 4-25. Added COMMA_ALIGN_LATENCY attribute to
Table 4-26. Updated description of GEARBOX_MODE attribute in Table 4-42. Added
Chapter 5, Board Design Guidelines. Updated all package drawings in Appendix A, Placement
Information by Package. Updated Table B-1.
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