Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 79
UG482 (v1.9) December 19, 2016
FPGA TX Interface
TXOUTCLK Driving GTP Transceiver TX in 2-Byte Mode
In Figure 3-2, TXOUTCLK is used to drive TXUSRCLK and TXUSRCLK2 for 2-byte mode
(TX_DATA_WIDTH = 16 or 20) in a single-lane configuration. The frequency of TXUSRCLK2 is
equal to TXUSRCLK.
Notes relevant to Figure 3-2:
1. BUFH can be used with certain limitations. For details about placement constraints and
restrictions on clocking resources (MMCM, BUFH, BUFG, etc.), refer to UG472
, 7Series
FPGAs Clocking Resources User Guide.
2. F
TXUSRCLK2
= F
TXUSRCLK
.
X-Ref Target - Figure 3-2
Figure 3-2: Single Lane—TXOUTCLK Drives TXUSRCLK2 (2-Byte Mode)
UG482_c3_02_110911
BUFG
1
2
7 Series FPGAs
GTP Transceiver
TXOUTCLK
TXUSRCLK2
2
TXUSRCLK
TXDATA (TX_DATA_WIDTH = 16 / 20 bits)
Design in
FPGA
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English