80 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 3: Transmitter
Similarly, Figure 3-3 shows the shows the same settings in multiple lanes configuration.
Notes relevant to Figure 3-3:
1. BUFH can be used with certain limitations. For details about placement constraints and
restrictions on clocking resources (MMCM, BUFH, BUFG, etc.), refer to UG472
, 7Series
FPGAs Clocking Resources User Guide.
2. F
TXUSRCLK2
= F
TXUSRCLK
.
X-Ref Target - Figure 3-3
Figure 3-3: Multiple Lanes—TXOUTCLK Drives TXUSRCLK2 (2-Byte Mode)
UG482_c3_03_110911
BUFG
1
2
7 Series FPGAs
GTP Transceiver
TXOUTCLK
TXUSRCLK2
2
TXUSRCLK
TXDATA (TX_DATA_WIDTH =
16 / 20 bits)
Design in
FPGA
2
7 Series FPGAs
GTP Transceiver
TXUSRCLK2
2
TXUSRCLK
TXDATA (TX_DATA_WIDTH = 16 / 20 bits)
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