Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 237
UG482 (v1.9) December 19, 2016
Appendix A
Placement Information by Package
This appendix provides the Quad position information for available device and package
combinations along with the pad numbers for the external signals associated with each serial
transceiver channel and the associated primitive. References to the XC part numbers also apply to
the XA and XQ part numbers, where available.
• CPG236 Package Placement Diagram, page 238
• CSG325 Package Placement Diagram, page 239
• CLG485 Package Placement Diagram, page 240
• FGG484 Package Placement Diagram, page 241
• FGG676 Package Placement Diagram, page 242
• FBG484 Package Placement Diagram, page 244
• SBG484 Package Placement Diagram, page 245
• FBG676 Package Placement Diagram, page 246
• FFG1156 Package Placement Diagram, page 248
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600