Xilinx 7 Series - FGG676 Package Placement Diagram

242 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Appendix A: Placement Information by Package
FGG676 Package Placement Diagram
Figure A-5 and Figure A-6 show the placement diagram for the FGG676 package.
X-Ref Target - Figure A-5
Figure A-5: Placement Diagram for the FGG676 Package (1 of 2)
D10 MGTPTXP3_216
C10 MGTPTXN3_216
D12 MGTPRXP3_216
C12 MGTPRXN3_216
B9 MGTPTXP2_216
UG482_aA_02_022614
A9 MGTPTXN2_216
B13 MGTPRXP2_216
A13 MGTPRXN2_216
F13 MGTREFCLK1P_216
E13 MGTREFCLK1N_216
F11 MGTREFCLK0P_216
E11 MGTREFCLK0N_216
D8 MGTPTXP1_216
C8 MGTPTXN1_216
D14 MGTPRXP1_216
C14 MGTPRXN1_216
B7 MGTPTXP0_216
A7 MGTPTXN0_216
B11 MGTPRXP0_216
A11 MGTPRXN0_216
XC7A75T:
GTPE2_CHANNEL_X0Y4
XC7A100T:
GTPE2_CHANNEL_X0Y4
XC7A75T:
GTPE2_CHANNEL_X0Y7
XC7A100T:
GTPE2_CHANNEL_X0Y7
XC7A75T:
GTPE2_CHANNEL_X0Y6
XC7A100T:
GTPE2_CHANNEL_X0Y6
XC7A75T:
GTPE2_CHANNEL_X0Y5
XC7A100T:
GTPE2_CHANNEL_X0Y5
XC7A75T:
GTPE2_COMMON_X0Y1
XC7A100T:
GTPE2_COMMON_X0Y1
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