Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 67
UG482 (v1.9) December 19, 2016
Dynamic Reconfiguration Port
Dynamic Reconfiguration Port
Functional Description
The dynamic reconfiguration port (DRP) allows the dynamic change of parameters of the
GTPE2_CHANNEL and GTPE2_COMMON primitives. The DRP interface is a processor-friendly
synchronous interface with an address bus (DRPADDR) and separated data buses for reading
(DRPDO) and writing (DRPDI) configuration data to the primitives. An enable signal (DRPEN), a
read/write signal (DRPWE), and a ready/valid signal (DRPRDY) are the control signals that
implement read and write operations, indicate operation completion, or indicate the availability of
data.
Ports and Attributes
Table 2-29 shows the DRP related ports for GTPE2_CHANNEL.
Table 2-30 shows the DRP related ports for GTPE2_COMMON.
Table 2-29: DRP Ports of GTPE2_CHANNEL
Port Dir Clock Domain Description
DRPADDR[8:0] In DRPCLK DRP address bus.
DRPCLK In N/A DRP interface clock.
DRPEN In DRPCLK DRP enable signal.
0: No read or write operation performed.
1: Enables a read or write operation.
For write operations, DRPWE and DRPEN must be
driven High for one DRPCLK cycle only (see
Figure 2-23 for correct operation). For read
operations, DRPEN must be driven High for one
DRPCLK cycle only (see Figure 2-24 for correct
operation.
DRPDI[15:0] In DRPCLK Data bus for writing configuration data from the
FPGA logic resources to the transceiver.
DRPRDY Out DRPCLK Indicates operation is complete for write operations
and data is valid for read operations. See Figure 2-23
and Figure 2-24 for the assertion of DRPRDY signal
after a write and a read operation.
DRPDO[15:0] Out DRPCLK Data bus for reading configuration data from the
GTP transceiver to the FPGA logic resources.
DRPWE In DRPCLK DRP write enable.
0: Read operation when DRPEN is 1.
1: Write operation when DRPEN is 1.
For write operations, DRPWE and DRPEN should be
driven High for one DRPCLK cycle only. See
Figure 2-23 for correct operation.
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Xilinx 7 Series Specifications

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Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English