Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 111
UG482 (v1.9) December 19, 2016
TX Phase Interpolator PPM Controller
Table 3-25 defines the attributes required for TX fabric clock output control.
TX Phase Interpolator PPM Controller
Functional Description
The TX Phase Interpolator Parts Per Million (TXPIPPM) Controller module provides support for
dynamically controlling the TX phase interpolator (TX PI). Located in the TX PCS, its inputs come
from the FPGA TX Interface and it outputs to the TX PMA. Applications exist that require fine-tune
control of the data in the TX PMA. Control of the output clock from the PLL is achieved through a
TX PI, which in turn can be controlled by the TX phase interpolator PPM controller module. The
FPGA logic can control the TX PI in the TX PMA through the use of the TX phase interpolator PPM
controller module in the PCS.
TXDLYBYPASS In Async TX delay alignment bypass:
0: Uses the TX delay alignment circuit.
Set to 1'b0 when the TX buffer is
bypassed.
1: Bypasses the TX delay alignment
circuit. Set to 1'b1 when the TX buffer
is used.
TXRATEMODE In Async Determines if TXRATE should be treated as
synchronous or asynchronous.
0: Synchronous. When set to 1'b0, an
automatic reset sequence occurs in
response to a change on the TXRATE
port.
1: Asynchronous.
Table 3-25: TX Fabric Clock Output Control Attributes
Attribute Type Description
TRANS_TIME_RATE 8-bit Hex Reserved. The recommended value from the
7 Series FPGAs Transceivers Wizard should be
used. This attribute determines when PHYSTATUS
and TXRATEDONE are asserted after a rate
change.
TXBUF_RESET_ON_RATE_C
HANGE
String When set to TRUE, this attribute enables an
automatic TX buffer reset during a rate change
event initiated by a change in TXRATE.
TXOUT_DIV Integer This attribute controls the setting for the TX serial
clock divider. This attribute is only valid when
TXRATE = 3'b000. Otherwise the D divider
value is controlled by TXRATE. Valid settings are
1, 2, 4, and 8.
Table 3-24: TX Fabric Clock Output Control Ports (Cont’d)
Port Dir Clock Domain Description
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English