Xilinx 7 Series User Manual

86 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 3: Transmitter
Enabling and Disabling 8B/10B Encoding
To enable the 8B/10B encoder, TX8B10BEN must be driven High. The TX 8B/10B encoder allows
byte interleaved data to bypass the encoder on a per-byte basis. When TX8B10BEN is driven Low,
all encoders are turned off and no data from TXDATA can be encoded. When TX8B10BEN is High,
driving a bit from TX8B10BBYPASS High can make the corresponding byte channel from
TXDATA bypass 8B/10B encoding. When the encoder is turned off, the operation of the TXDATA
port is as described in the FPGA TX interface.
TX Gearbox
Functional Description
Some high-speed data rate protocols use 64B/66B encoding to reduce the overhead of 8B/10B
encoding while retaining the benefits of an encoding scheme. The TX gearbox provides support for
64B/66B and 64B/67B header and payload combining. The Interlaken interface protocol
specification uses the 64B/67B encoding scheme. Refer to the Interlaken specification for further
information. The Interlaken specification can be downloaded from: http://
www.interlakenalliance.com/.
The TX gearbox supports 2-byte and 4-byte interfaces. Scrambling of the data is done in the FPGA
logic.
Ports and Attributes
Table 3-8 defines the TX gearbox ports.
Table 3-8: TX Gearbox Ports
Port Name Dir Clock Domain Description
TXGEARBOXREADY Out TXUSRCLK2 This output indicates if data can be
applied to the 64B/66B or 64B/67B
gearbox when GEARBOX_MODE is
set to use the gearbox.
0: No data can be applied
1: Data must be applied
TXHEADER[2:0] In TXUSRCLK2 These ports are the header inputs. [1:0]
are used for the 64B/66B gearbox, and
[2:0] are used for the 64B/67B gearbox.
TXSEQUENCE[6:0] In TXUSRCLK2 These inputs are used for the fabric
sequence counter when the TX gearbox
is used. [5:0] are used for the 64B/66B
gearbox, and [6:0] are used for the 64B/
67B gearbox.
TXSTARTSEQ In TXUSRCLK2 This input indicates the first word to be
applied after reset for the 64B/66B or
64B/67B gearbox.
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600