Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 81
UG482 (v1.9) December 19, 2016
FPGA TX Interface
TXOUTCLK Driving GTP Transceiver TX in 4-Byte Mode
In Figure 3-4, TXOUTCLK is used to drive TXUSRCLK2 for 4-byte mode (TX_DATA_WIDTH =
32 or 40). The frequency of TXUSRCLK2 is equal to half of the frequency of TXUSRCLK.
MMCMs or PLLs, which are part of the clock management tiles (CMTs) located in the top half of
the device, can only drive the BUFGs in the top half of the devices. Similarly, MMCMs or PLLs
located in the bottom half can only drive BUFGs in the bottom half.
Notes relevant to Figure 3-4:
1. F
TXUSRCLK2
= F
TXUSRCLK
/2
2. In the XC7A200T device, BUFH can be used with certain limitations. For details about
placement constraints and restrictions on clocking resources (MMCM, BUFH, BUFG, etc.),
refer to UG472
, 7 Series FPGAs Clocking Resources User Guide.
X-Ref Target - Figure 3-4
Figure 3-4: Single Lane—TXOUTCLK Drives TXUSRCLK2 (4-Byte Mode)
UG482_c3_04_041012
BUFG
or BUFH
1
7 Series FPGAs
GTP Transceiver
TXOUTCLK
TXUSRCLK2
CLKIN
1
TXUSRCLK
TXDATA (32 / 40 bits)
Design in
FPGA
MMCME2
or
PLLE2
BUFG
2
CLKOUT0
BUFG
2
CLKOUT1
LOCKED
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600