Xilinx 7 Series User Manual

154 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
Ports and Attributes
Table 4-19 defines ports related to the RX eye scan function.
Table 4-20 defines RX eye scan attributes. Lower case attribute names indicate R/O.
Table 4-19: RX Margin Analysis Ports
Port Dir Domain Description
EYESCANDATAERROR Out async Asserts high for one REC_CLK cycle when
an (unmasked) error occurs while in the
COUNT or ARMED state.
EYESCANTRIGGER In RXUSRCLK2 Causes a trigger event.
See ES_CONTROL[4] below.
RXRATE In RXUSRCLK2 This port dynamically controls the setting for
the RX serial clock divider D (see Table 4-16)
and it is used with RXOUT_DIV attribute.
3'b000: Use RXOUT_DIV divider value
3'b001: Set D divider to 1
3'b010: Set D divider to 2
3'b011: Set D divider to 4
3'b100: Set D divider to 8
Table 4-20: RX Margin Analysis Attributes
Attribute Type Description
ES_VERT_OFFSET 9-bit
Binary
Controls the vertical (differential voltage) offset of the scan sample:
[6:0]: Offset magnitude.
[7]: Offset sign (1 is negative, 0 is positive).
ES_HORZ_OFFSET 12-bit
Hex
Controls the horizontal (phase) offset of the scan sample.
[10:0]: Phase offset (two's complement). The center of data eye (0 UI) corresponds to a count
of 11'd0 for all data rates. The table below lists the minimum count (representing -0.5 UI)
and maximum count (representing +0.5 UI) for each data rate.
Rate min count [dec(bin)] eye center [dec(bin)] max count [dec(bin)]
Full -32 (11'b11111100000) +0(11'b00000000000) +32(11'b00000100000)
Half -64 (11'b11111000000) +0(11'b00000000000) +64(11'b00001000000)
Qrtr -128 (11'b11110000000) +0(11'b00000000000) +128(11'b00010000000)
Octal -256 (11'b11100000000) +0(11'b00000000000) +256(11'b00100000000)
[11]: Phase unification. Must be set to 0 for all positive counts (including zero) and to 1 for all
negative counts.
ES_PRESCALE 5-bit
Binary
Controls the pre-scaling of the sample count to keep both sample count and error count in
reasonable precision within the 16-bit register range. Prescale = 2
(1 + register value)
, so minimum
prescale is 2
(1+0)
= 2 and maximum prescale is 2
(1+31)
= 4,284,967,296.
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Xilinx 7 Series Specifications

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Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English