Xilinx 7 Series

UG482 (v1.9) December 19, 2016 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
10/23/2012 1.3 Added Artix-7 device in Functional Description, page 25, Single External Reference Clock Use
Model, page 32, and Multiple External Reference Clock Use Model, page 33. Deleted
XC7A350T in Figure 3-4 and Figure 3-5 footnotes. Deleted PCIe Protocol in Table 4-3. Deleted
XC7A350T devices in Table 5-2 and Figure 5-3. Added additional ceramic filter capacitor to
MGTAVCC_G[N} and MGTAVTT_G[N] pins in Table 5-14. Deleted XC7A350T in Figure A-9,
Figure A-10, Figure A-11, Figure A-12, Figure A-13, and Figure A-14. Deleted XC7A350T in
Table B-1.
02/21/2013 1.4 Replaced references to GTX transceiver with references to GTP transceiver throughout
document.
Chapter 2: Updated Figure 2-2, Figure 2-12, Figure 2-13, Figure 2-14, Figure 2-15, Figure 2-16,
and Figure 2-17. Updated Table 2-6, rows one and two, and Table 2-8, rows one and four. Revised
Reset and Initialization, last paragraph on page 40. Updated Table 2-14, rows five and six. Added
Table 2-17, and sections After Power-up and Configuration, page 47, through TX Parallel Clock
Source Reset, page 47. Updated Table 2-18, rows two, three, four, seven, twelve, thirteen, fifteen,
and seventeen. Updated Figure 2-19 and added notes relevant to the figure. Updated Figure 2-20
and added notes relevant to the figure. Added GTP Transceiver RX PMA Reset, page 56,
including Figure 2-21 and notes relevant to the figure. Revised GTP Transceiver RX Component
Resets, page 56 by adding Table 2-22 and sections After Power-up and Configuration, page 47
through After Comma Realignment, page 61. Revised Loopback Functional description on
page 65. Updated Table 2-28, row two. Updated Table 2-29
, rows three and seven and Table 2-30,
rows three and seven. Added Digital Monitor, page 70 through page 75.
Chapter 3: Revised section TX Buffer Bypass, page 95 through page 106. Updated Figure 3-20.
Updated Table 3-24, rows three and five, and Table 3-24, row three.
Chapter 4: Updated Table 4-3, Table 4-4, Table 4-5, Table 4-6, rows five and six, and Table 4-7,
row twelve. Added Use Mode, page 132 through Figure 4-14, page 138. Added section Use
Modes, page 144 through Table 4-15. Updated Figure 4-18. Updated Table 4-17, rows three and
five. Added section Using RXRATE, page 149 through page 150. Revised section RX Buffer
Bypass, page 173 through page 186. Updated Table 4-33 and Table 4-33, rows five and ten.
Chapter 5: Updated Table 5-2, rows one and two, and Table 5-11, rows three and four.
Appendix A: Updated Figure A-4 through Figure A-14.
Appendix B: Updated Table B-1.
04/15/2013 1.5 Added last two rows in Table 2-22. Added three sentences to Loopback Functional Description,
page 25. Changed “DEN” to “DRPEN” in Table 2-29 and Table 2-30. Added a note to
Figure 2-23 and Figure 2-24. Revised TX Buffer Bypass Functional Description, page 93 and
Table 3-15. Revised TX Buffer Bypass Use Modes, page 98, deleted Figure 3-12, TX Buffer
Bypass, Single lane Auto mode Port Connection, and replaced Figure 3-12 and notes relevant to
it. Revised Using TX Buffer Bypass in Multi-Lane Mode, page 100 (and removed “Manual” from
section title and text). Deleted section titled “Using TX Buffer Bypass in Multi Lane Auto Mode.”
Added last two rows to Table 4-2. Changed “INCP” to “IPCM” in Table 4-3, Table 4-4, and
Table 4-5. Changed RXCDR_CFG attribute type from 72- to 83-bit hex in Table 4-12.
08/28/2013 1.6 Added devices XC7A35T-CSG325 (Preliminary), XC7A35T-FGG484 (Preliminary),
XC7A50T-CSG325 (Preliminary), XC7A50T-FGG484 (Preliminary), XC7A75T-FGG484, and
XC7A75T-FGG676.
Date Version Revision