Xilinx 7 Series User Manual

40 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 2: Shared Features
For major coverage differences between initialization and component resets, refer to Table 2-16 for
the GTP transceiver’s TX and Table 2-20 and Table 2-21 for the GTP transceiver’s RX.
All reset ports described in this section initiate the internal reset state machine when driven High.
The internal reset state machines are held in the reset state until these same reset ports are driven
Low. These resets are all asynchronous. The guideline for the pulse width of these asynchronous
resets is one period of the reference clock, unless otherwise noted.
Note:
Reset ports should not be used for the purpose of power down. For details on proper power
down usage, refer to Power Down.
Reset Modes
The GTP transceiver’s RX resets can operate in two different modes: Sequential mode and single
mode. The GTP transceiver’s TX resets can operate only in sequential mode.
• Sequential mode: The reset state machine starts with an initialization or component reset input
driven High and proceeds through all states after the requested reset states in the reset state
machine, as shown in Figure 2-13 for the GTP transceiver’s TX or Figure 2-18 for the GTP
transceiver’s RX until completion. The completion of sequential mode reset flow is signaled
when (TX/RX)RESETDONE transitions from Low to High.
• Single mode: The reset state machine only executes the requested component reset
independently for a predetermined time set by its attribute. It does not process any state after
the requested state, as shown in Figure 2-18 for the GTP transceiver’s RX. The requested reset
can be any component reset to reset the PMA, the PCS, or functional blocks inside them. The
completion of a single mode reset is signaled when RXRESETDONE transitions from Low to
High.
The GTP transceiver initialization reset must use sequential mode. All component resets can be
operated in either sequential mode or single mode, except for TX resets, which can only operate in
sequential mode.
The GTP transceiver uses GTRESETSEL to select between sequential reset mode and single reset
mode. Table 2-10 provides configuration details that apply to both the GTP transceiver’s TX and
RX. Reset modes have no impact on PLL0 or PLL1 resets. During normal operation, the GTP
transceiver’s TX or RX can be reset by applications in either sequential mode or single mode (GTP
transceiver’s RX only), which provides flexibility to reset a portion of the GTP transceiver. When
using either sequential mode or single mode, RESETOVRD must be driven Low, as shown in
Table 2-10. RESETOVRD and GTRESETSEL must be set to the desired value 300–500 ns before
the assertions of any reset.
Table 2-10: GTP Transceiver Reset Modes Operation
Operation Mode RESETOVRD GTRESETSEL
Sequential Mode 00
Single Mode 01
Table 2-11: GTP Transceiver Reset Mode Ports
Port Dir Clock Domain Description
GTRESETSEL In Async Reset mode enable port.
Low: Sequential mode (recommended).
High: Single mode.
RESETOVRD In Async Reserved. Must be tied to ground.
Send Feedback

Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600