Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 57
UG482 (v1.9) December 19, 2016
Reset and Initialization
Table 2-20: RX Component Reset Coverage in Sequential Mode
Functional Blocks
GTRX
RESET
RXPMA
RESET
RXLPM
RESET
EYESCAN
RESET
RXPCS
RESET
RXBUF
RESET
RX PCS
FPGA RX Fabric
Interface
√√√√√
RX Gearbox
√√√√√
RX Status Control
√√√√√
RX Elastic Buffer
Delay Aligner
√√√√√
RX 8B/10B Encoder
√√√√√
RX Comma Detect and
Alignment
√√√√√
RX Polarity
√√√√√
PRBS Checker
√√√√√
RX Elastic Buffer
√√√√√√
RX Reset FSM
√
RX PMA
RX Analog Front End
√√
RX Out-of-Band
Signaling
√√
RX SIPO
√√
RX CDR Phase Path
√√
RX CDR Frequency
Path
√√
RX LPM
√√ √
RX ISCAN
√√ √ √
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600