Xilinx 7 Series User Manual

144 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
Use Modes
RX CDR Lock to Reference
To get the CDR to lock to reference set RXCDRHOLD = 1'b1 and set RXCDROVRDEN = 1'b0
Dynamically Changing RX CDR Settings for Line Rate and Selected Protocol
Changes
The sequence of events to dynamically change the RX CDR settings is described here. It pertains
only to changes for the CDR:
1. When ready (i.e., all valid data is flushed out of the receiver datapath), use the DRP to
implement changes to the CDR loop filter settings with the attribute RXCDR_CFG[83:0].
Recommended settings for this attribute are provided in Table 4-13, Table 4-14, and Table 4-15.
2. Provide the changes via ports PLL[0/1]REFCLKSEL and/or the DRP to the attributes listed in
Table 2-9, page 35.
3. Follow the reset guidelines as detailed in PLL Reset, page 41.
4. When the PLL has locked, assert GTRXRESET and follow the guidelines detailed in GTP
Transceiver TX Reset in Response to GTTXRESET Pulse, page 44.
5. After the RXRESETDONE signal goes High, correct data must be verified before continuing
with the operation of the transceiver (i.e., check a known data pattern).
Dynamically Changing RX CDR Settings to Tune CDR Loop Filter Settings
Only
1. When ready (all valid data flushed out of receiver datapath), use the DRP to implement changes
to the CDR loop filter settings with the attribute RXCDR_CFG[83:0]. Recommended settings
for this attribute are provided in Table 4-13, Table 4-14, and Table 4-15.
2. Assert the GTRXRESET port and follow the guidelines detailed in GTP Transceiver RX Reset
in Response to GTRXRESET Pulse, page 54.
After the RXRESETDONE signal goes High, correct data must be verified before continuing with
the operation of the transceiver (i.e., check a known data pattern).
RXCDR_PH_RESET_ON_EIDLE Binary Enables automatic reset of the CDR phase
during the optional PCI Express reset
sequence during electrical idle.
RX_OS_CFG[12:0] 13-bit Binary Reserved. The recommended value from
the 7 Series FPGAs Transceivers Wizard
should be used.
Table 4-12: CDR Attributes (Cont’d)
Attribute Type Description
Table 4-13: CDR Recommended Settings for Scrambled/PRBS Data
(1)
(No SSC
(2)
)
RXOUT_DIV REFCLK PPM RXCDR_CFG
1
±200
83'h0_0011_07FE_2060_2104_1010±700
±1,250
Send Feedback

Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600