Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 145
UG482 (v1.9) December 19, 2016
RX CDR
2
±200
83'h0_0011_07FE_2060_2108_1010±700
±1,250
4 or 8
±200
83'h0_0011_07FE_0860_2110_1010±700
±1,250
Notes:
1. For protocol-specific settings, use the recommended value from the 7 Series FPGAs Transceivers Wizard and/or
the protocol characterization reports.
2. Spread-spectrum clocking (SSC) is used to reduce the spectral density of electromagnetic interference (EMI).
Table 4-14: CDR Recommended Settings for Protocols with SSC
RXOUT_DIV REFCLK PPM with SSC RXCDR_CFG
1
±700 PPM SSC 33 KHz Triangular
-5,000 PPM
83'h0_0000_87FE_2060_2448_1010
2 83'h0_0000_47FE_2060_2450_1010
4 83'h0_0000_47FE_1060_2450_1010
Table 4-15: GTP CDR Recommended Settings for 8B/10B Encoded Data
(1)
(No
SSC
(2)
)
RXOUT_DIV REFCLK PPM RXCDR_CFG
1
±200 83'h0_0001_07FE_4060_0104_1010
±700
83'h0_0001_07FE_4060_2104_1010
±1,250
2
±200 83'h0_0001_07FE_2060_0104_1010
±700
83'h0_0001_07FE_2060_2104_1010
±1,250
4
±200 83'h0_0001_07FE_1060_0104_1010
±700
83'h0_0001_07FE_1060_2104_1010
±1,250
8
±200 83'h0_0001_07FE_0860_0104_1010
±700
83'h0_0001_07FE_0860_2104_1010
±1,250
Notes:
1. For protocol-specific settings, use the recommended value from the 7 Series FPGAs Transceivers Wizard and/or
the protocol characterization reports.
2. Spread-spectrum clocking (SSC) is used to reduce the spectral density of electromagnetic interference (EMI).
3. RX_DEBUG_CFG is 14'h000 for all settings.
Table 4-13: CDR Recommended Settings for Scrambled/PRBS Data
(1)
(No SSC
(2)
)
RXOUT_DIV REFCLK PPM RXCDR_CFG
Send Feedback

Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English