7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 35
UG482 (v1.9) December 19, 2016
PLL
The PLL input clock selection is described in Reference Clock Selection and Distribution, page 25.
The PLL outputs feed the TX and RX clock divider blocks, which control the generation of serial
and parallel clocks used by the PMA and PCS blocks.
Figure 2-10 illustrates a conceptual view of the PLL architecture. The input clock can be divided by
a factor of M before feeding into the phase frequency detector. The feedback dividers N1 and N2
determine the VCO multiplication ratio and the PLL output frequency. A lock indicator block
compares the frequencies of the reference clock and the VCO feedback clock to determine if a
frequency lock has been achieved.
The PLL has a nominal operating range between 1.6 GHz to 3.3 GHz. The 7 Series FPGAs
Transceivers Wizard chooses the appropriate PLL settings based on application requirements.
Equation 2-1 shows how to determine the PLL output frequency (GHz).
Equation 2-1
Equation 2-2 shows how to determine the line rate (Gb/s). D represents the value of the TX or RX
clock divider block in the channel.
Equation 2-2
X-Ref Target - Figure 2-9
Figure 2-9: Internal Clocking Architecture
X-Ref Target - Figure 2-10
Figure 2-10: PLL Block Diagram
UG482_c2_09_110811
TX
Clock
Dividers
TX PMA
TX PCS
RX PMA
RX PCS
RX
Clock
Dividers
GTPE2_CHANNEL
PLL0
REFCLK
Distribution
PLL1
GTPE2_COMMON
PLL
CLKIN
/ M
Lock
Indicator
Phase
Frequency
Detector
Charge
Pump
Loop
Filter
VCO
PLL
LOCKED
PLL
CLKOUT
/ N1
UG482_c2_10_011612
/ N2
f
PLLClkout
f
PLLClkin
N1 N2×
M
---------------------×=
f
LineRate
f
PLLClkout
2×
D
-----------------------------------=
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