Xilinx 7 Series

36 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 2: Shared Features
Table 2-7 lists the allowable divider settings.
Ports and Attributes
Table 2-8 and Table 2-9 defines the ports and attributes for the PLL.
Table 2-7: PLL Divider Settings
Factor Attribute Valid Settings
M PLL0_REFCLK_DIV
PLL1_REFCLK_DIV
1, 2
N2 PLL0_FBDIV
PLL1_FBDIV
1, 2, 3, 4, 5
N1 PLL0_FBDIV_45
PLL1_FBDIV_45
4, 5
DRXOUT_DIV
TXOUT_DIV
1, 2, 4, 8
Table 2-8: PLL Ports
Port Direction Clock Domain Description
PLL0LOCKDETCLK
PLL1LOCKDETCLK
In Clock Stable reference clock for the detection of the feedback and
reference clock signals to the PLL. The input reference
clock to the PLL or any output clock generated from the
PLL (e.g., TXOUTCLK) must not be used to drive this
clock.
This clock is required only when using the
PLL[0/1]FBCLKLOST and PLL[0/1]REFCLKLOST
ports. It does not affect the PLL lock detection, reset, and
power-down functions.
PLL0LOCKEN
PLL1LOCKEN
In Async This port enables the PLL lock detector. It must always be
tied High.
PLL0PD
PLL1PD
In Async Active-High signal that powers down the PLL for power
savings.
BGBYPASSB In Async Reserved. This port must be set to 1'b1. This value should
not be modified.
BGMONITORENB In Async Reserved. This port must be set to 1'b1. This value should
not be modified.
BGPDB In Async Reserved. This port must be set to 1'b1. This value should
not be modified.
BGRCALOVRD[4:0] In Async Reserved. This port must be set to 5'b111111. This value
should not be modified.
RCALENB In Async Reserved. This port must be set to 1'b1. This value should
not be modified.
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