Xilinx 7 Series User Manual

96 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 3: Transmitter
Table 3-15: TX Buffer Bypass Ports
Port Dir Clock Domain Description
TXPHDLYRESET In Async TX phase alignment hard reset. Forces TXOUTCLK to the center of the delay
alignment tap. The delay alignment tap has a full range of ±4 ns and a half range
of ±2 ns. The user is recommended to use TXDLYSRESET only for phase and
delay alignment.
TXPHALIGN In Async Sets the TX phase alignment.
TXPHALIGNEN In Async Enables the TX phase alignment.
TXPHDLYPD In Async TX phase and delay alignment circuit power down. TXPHDLYPD is tied High
when:
• TX buffer bypass is not in use.
• TXPD is asserted.
• TXOUTCLKSEL is set to 3'b011or 3'b100 but the reference clock is
not connected.
TXPHDLYPD is tied Low during TX buffer bypass mode normal operation.
0: Power-up the TX phase and delay alignment circuit.
1: Power-down the TX phase and delay alignment circuit.
TXPHINIT In Async TX phase alignment initialization.
TXPHOVRDEN In Async TX phase alignment counter override enable. Tied Low when not in use.
0: Normal operation.
1: Enables TX phase alignment counter override with the value from
TXPH_CFG[10:0].
TXDLYSRESET In Async TX delay alignment soft reset to gradually shift TXOUTCLK to the center of
the delay alignment tap. The delay alignment tap has a full range of ±4 ns and
a half range of ±2 ns. TXPHDLYRESET and GTTXRESET force
TXOUTCLK to the center of the delay alignment tap which might cause a
sudden phase shift within one clock cycle. Use TXPMARESET followed by
TXDLYSRESET to reset the transmitter and restart phase alignment without
sudden phase shifts on TXOUTCLK.
TXDLYBYPASS In Async TX delay alignment bypass.
0: Uses the TX delay alignment circuit.
1: Bypasses the TX delay alignment circuit.
TXDLYEN In Async Enables the TX delay alignment.
TXDLYOVRDEN In Async TX delay alignment counter override enable. Tied Low when not in use.
0: Normal operation.
1: Enables TX delay alignment counter override with the value from
TXDLY_CFG[14:6].
TXPHDLYTSTCLK In Async TX phase and delay alignment test clock. Used with TXDLYHOLD and
TXDLYUPDOWN.
TXDLYHOLD In TXPHDLYTSTCLK TX delay alignment hold. Used as a hold override when
TXPHDLY_CFG[1] = 1 to bypass the TX phase and delay alignment voter.
Tied Low when not in use.
TXDLYUPDOWN In TXPHDLYTSTCLK TX delay alignment up or down. Used as an up or down override when
TXPHDLY_CFG[1] = 1 to bypass the TX phase and delay alignment voter.
Tied Low when not in use.
TXPHALIGNDONE Out Async TX phase alignment done.
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English