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Xilinx 7 Series User Manual

Xilinx 7 Series
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7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 97
UG482 (v1.9) December 19, 2016
TX Buffer Bypass
TXPHINITDONE Out Async Indicates that TX phase alignment initialization is done.
TXDLYSRESETDONE Out Async Indicates that TX delay alignment soft reset is done.
TXSYNCMODE In Async Reserved. Tie to GND.
TXSYNCALLIN In Async Reserved. Tie to GND.
TXSYNCIN In Async Reserved. Tie to GND.
TXSYNCOUT Out Async Reserved.
TXSYNCDONE Out Async Reserved.
Table 3-15: TX Buffer Bypass Ports (Cont’d)
Port Dir Clock Domain Description
Table 3-16: TX Buffer Attributes
Attribute Type Description
TXBUF_EN String Use or bypass the TX buffer.
TRUE: Uses the TX buffer (default).
FALSE: Bypasses the TX buffer (advanced feature).
TX_XCLK_SEL String Selects the clock source used to drive the PMA parallel clock domain (XCLK).
TXOUT: Selects TXOUTCLK as the source of XCLK. Used when using the
TX buffer.
TXUSR: Selects TXUSRCLK as the source of XCLK. Used when bypassing the
TX buffer.
TXPH_CFG 16-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
TXPH_MONITOR_SEL 5-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
TXPHDLY_CFG 24-bit Binary TX phase and delay alignment configuration.
TXPHDLY_CFG[19] = 1 is used to set the TX delay alignment tap to the full range
of ±4 ns.
TXPHDLY_CFG[19] = 0 is used to set the TX delay alignment tap to the half range
of ±2 ns.
Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
TXDLY_CFG 16-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
TXDLY_LCFG 9-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
TXDLY_TAP_CFG 16-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
TXSYNC_MULTILANE 1-bit Binary Reserved. Tie to 1'b0.
TXSYNC_SKIP_DA 1-bit Binary Reserved. Tie to 1'b0.
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Xilinx 7 Series Specifications

General IconGeneral
BrandXilinx
Model7 Series
CategoryComputer Hardware
LanguageEnglish

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