Xilinx 7 Series - Page 32

32 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 2: Shared Features
Single External Reference Clock Use Model
In the single external reference clock use model, the user connects the IBUFDS_GTE2 output (O) to
the GTREFCLK0 input port of the GTPE2_COMMON primitive. The user design can leave the
other unused reference clock ports floating. The IBUFDS_GTE2 input pins can be constrained in
the user constraints file (UCF). Figure 2-5 shows a single GTPE2_COMMON primitive connected
to a single IBUFDS_GTE2 primitive.
X-Ref Target - Figure 2-4
Figure 2-4: External Reference Clock Use Case
UG482_c2_04_110811
TX
RX
GTPE2_CHANNEL
PLL0
PLL1
GTPE2_COMMON
IBUFDS_GTE2
GTREFCLK0
IBUFDS_GTE2
GTREFCLK1
0
1
0
1
TXSYSCLKSEL[0]
PLL0CLKPLL0OUTCLK
PLL0OUTREFCLK
PLL1OUTREFCLK
PLL1CLK
PLL0REFCLK
PLL1REFCLK
PLL1OUTCLK
RXSYSCLKSEL[0]
0
1
0
1
TXSYSCLKSEL[1] TXOUTCLKSEL
TXOUTCLK
RXOUTCLK
RXSYSCLKSEL[1] RXOUTCLKSEL
X-Ref Target - Figure 2-5
Figure 2-5: Single GTP Quad with a Single Local Reference Clock
UG482_c2_05_110811
GTPE2_
CHANNEL
GTREFCLK0
GTPE2_COMMON
GTPE2_
CHANNEL
GTPE2_
CHANNEL
GTPE2_
CHANNEL
GTP Quad
IBUFDS_GTE2
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