7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 99
UG482 (v1.9) December 19, 2016
TX Buffer Bypass
Figure 3-12 shows the required steps to perform the TX phase alignment and use the TX delay
alignment to adjust TXUSRCLK to compensate for temperature and voltage variations.
Notes relevant to Figure 3-12:
1. The sequence of events in Figure 3-12 is not drawn to scale.
2. Set the TXSYNC_OVRD attribute to 1'b1.
3. Set TXPHDLYRESET and TXDLYBYPASS to Low for all lanes.
4. Set TXPHALIGNEN to High.
5. Assert TXDLYSRESET. Hold this signal High until TXDLYSRESETDONE is asserted.
6. Deassert TXDLYSRESET after TXDLYSRESETDONE is asserted.
7. When TXDLYSRESET is deasserted, assert TXPHINIT. Hold this signal High until the rising
edge of TXPHINITDONE is observed.
8. Deassert TXPHINIT.
9. Assert TXPHALIGN. Hold this signal High until the rising edge of TXPHALIGNDONE is
observed.
10. Deassert TXPHALIGN.
11. Assert TXDLYEN. This causes TXPHALIGNDONE to be deasserted.
12. Hold TXDLYEN until the rising edge of TXPHALIGNDONE is observed.
13. TX delay alignment continues to adjust TXUSRCLK to compensate for temperature and
voltage variations.
Using the TX Phase Alignment to Minimize the TX Lane-to-Lane Skew
The TX phase alignment circuit can also be used to minimize skew between GTP transceivers.
Figure 3-13 shows how the TX phase alignment circuit can reduce lane skew by aligning the XCLK
domains of multiple GTP transceivers to a common clock source. Figure 3-22 shows multiple GTP
transceiver lanes running before and after TX phase is aligned to a common clock. Before the TX
phase alignment, all XCLKs have an arbitrary phase difference. After TX phase alignment, the only
phase difference is the skew from the common clock, and all lanes transmit data simultaneously as
long as the datapath latency is matched. TXUSRCLK and TXUSRCLK2 for all GTP transceivers
must come from the same source and must be routed through a low skew clocking resource such as
a BUFG for the TX phase alignment circuit to be effective.
X-Ref Target - Figure 3-12
Figure 3-12: TX Buffer Bypass Example, Single Lane Mode
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