Xilinx 7 Series - Page 138

138 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
X-Ref Target - Figure 4-13
Figure 4-13: Flowchart for Exit from RX Electrical Idle for PCIe Gen2
X-Ref Target - Figure 4-14
Figure 4-14: Flowchart for SATA 3G or SATA 6G
RX is Out of Electrical Idle
Is RXELECIDLE
Deasserted?
Valid EIOS?
PCIe Gen2 Exit
UG482_c4_113_020413
No
Ye s
No
Ye s
RX is in Electrical Idle
RX is Not in Electrical Idle
Is RXELECIDLE
Asserted?
Is Incoming Data
Valid?
SATA 3G or 6G
UG482_c4_114_020413
No
Ye s
Ye s
No
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