Xilinx 7 Series

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 137
UG482 (v1.9) December 19, 2016
RX Out-of-Band Signaling
X-Ref Target - Figure 4-11
Figure 4-11: Flowchart for PCIe Gen2
X-Ref Target - Figure 4-12
Figure 4-12: Flowchart for Entry to RX Electrical Idle for PCIe Gen2
RX is in Electrical Idle
RX is Not in Electrical Idle
Is RXELECIDLE
Asserted?
Is Incoming Data
Valid?
PCIe Gen2
UG482_c4_111_020413
No
Ye s
Ye s
No
RX is in Electrical Idle
Is EIOS
Detected?
Is RXELECIDLE
Detected?
PCIe Gen2 Entry
UG476_c4_113_080712
No
Ye s
No
Ye s
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