Xilinx 7 Series - Page 136

136 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
Notes:
1. The attributes pertaining to LPM, and CDR are:
• RXCDR_HOLD_DURING_EIDLE
• RXCDR_FR_RESET_ON_EIDLE
• RXCDR_PH_RESET_ON_EIDLE
• RX_LPM_HOLD_DURING_EIDLE
• RXBUF_RESET_ON_EIDLE
• RXBUF_EIDLE_HI_CNT
• RXBUF_EIDLE_LO_CNT
X-Ref Target - Figure 4-10
Figure 4-10: Flowchart for PCIe Gen1
Table 4-8: OOB Guidelines for Operating Rates above 1.5 Gb/s (Cont’d)
Protocol Operation
RX is in Electrical Idle
RX is in Electrical Idle
Is Scrambler
Present?
Is RXELECIDLE
Asserted?
PCIe Gen1
UG482_c4_111_020413
NoYe s
No
Ye s
RX is Not in Electrical Idle
Is RXELECIDLE
Asserted?
No
Ye s
Is Incoming Data
Valid?
Ye sNo
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