Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 135
UG482 (v1.9) December 19, 2016
RX Out-of-Band Signaling
Table 4-8: OOB Guidelines for Operating Rates above 1.5 Gb/s
Protocol Operation
PCIe Gen1 See Figure 4-10 for the algorithm to determine whether the
RX is in electrical idle.
If a scrambler has not been used, the RX electrical idle
should not be used for internal detect logic of the hold/reset
logic of the LPM, or CDR
(1)
. The user needs to verify
received data to decide whether or not an electrical idle state
is present i.e., qualification using incoming data is essential
in this mode of operation.
If a scrambler is used, electrical idle may solely be used to
determine whether the RX is in electrical idle.
PCIe Gen2 See Figure 4-11 for the algorithm to determine whether the
RX is in electrical idle. Other methods that can be used for
this are shown in Figure 4-12 and Figure 4-13.
RX electrical idle should not be used for internal detect logic
of the hold/reset logic of the LPM, or CDR
(1)
. The user needs
to verify received data to decide whether or not an electrical
idle state is present i.e., qualification using incoming data is
essential in this mode of operation.
SATA 1.5 Gb/s Use
Equation 4-1 to derive the appropriate OOB clock (see
Figure 4-9).
SATA 3 Gb/s See Figure 4-14 for the algorithm to determine whether the
RX is in electrical idle.
RX electrical idle should not be used for internal detect logic
of the hold/reset logic of the LPM, or CDR
(1)
. The user needs
to verify received data to decide whether or not an electrical
idle state is present i.e., qualification using incoming data is
essential in this mode of operation.
SATA 6 Gb/s See
Figure 4-14 for the algorithm to determine whether the
RX is in electrical idle.
RX electrical idle should not be used for internal detect logic
of the hold/reset logic of the LPM, or CDR
(1)
. The user needs
to verify received data to decide whether or not an electrical
idle state is present i.e., qualification using incoming data is
essential in this mode of operation.
PCIe Gen2 See Figure 4-12 and Figure 4-13 for the algorithm to
determine whether the RX is in electrical idle.
While entering and exiting electrical idle, the EIOS detection
must be used along with RXELECIDLE assertion to
determine whether the RX is in electrical idle.
RX electrical idle should not be used for internal detect logic
of the hold/reset logic of the LPM, or CDR
(1)
. The user needs
to verify received data to decide whether or not an electrical
idle state is present i.e., qualification using incoming data is
essential in this mode of operation.
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600