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Xilinx 7 Series User Manual

Xilinx 7 Series
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7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 129
UG482 (v1.9) December 19, 2016
RX Analog Front End
Table 4-4: Use Mode 2—RX Termination
Use
Mode
External AC
Coupling
Term
Voltage
Max Swing
mV
DPP
Suggested Protocols and Usage
Notes
2 On AVTT 1,200
Protocols:
Backplane
CEI-6 (1,200 mV
DPP
)
•Wireless
Serial RapidIO
Attribute Settings:
RX_CM_SEL[1:0] = 2'b00
RXLPM_INCM_CFG = 1'b1
RXLPM_IPCM_CFG = 1'b0
X-Ref Target - Figure 4-4
Figure 4-4: Use Mode 2
+
~100 nF
50Ω
50Ω
~100 nF
FPGABOARD
ACJTAG RX
ACJTAG RX
MGTAVTT
MGTAVTT
MGTAVTT
RX_CM_SEL [1:0] = 2'b11
UG482_c4_04_110911
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Xilinx 7 Series Specifications

General IconGeneral
Process Technology28nm
TransceiversUp to 96
I/O PinsUp to 1, 200
Transceiver Data RateUp to 28.05 Gbps
Power ConsumptionVaries by device
Operating TemperatureCommercial, Industrial
Package OptionsBGA, CSP
FamilyArtix-7, Kintex-7, Virtex-7
DSP Slices16 - 3600

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