Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 265
UG482 (v1.9) December 19, 2016
Appendix D
DRP Address Map of the GTP Transceiver
Table D-1 lists the DRP map of the GTPE2_COMMON primitive sorted by address.
Note:
The reserved bits should NOT be modified. Attributes that are not described explicitly are set
automatically by the 7 Series FPGAs Transceivers Wizard. These attributes must be left at their
defaults, except for use cases that explicitly request different values.
Table D-1: DRP Map of GTPE2_COMMON Primitive
DRP Address
(Hex)
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP Binary
Encoding
0002 15:0 R/W PLL0_CFG 15:0 0–65535 0–65535
0003 10:0 R/W PLL0_CFG 26:16 0–2047 0–2047
0004 13:9 R/W PLL0_REFCLK_DIV 4:0
116
20
0004 7 R/W PLL0_FBDIV_45 0
40
51
0004 5.0 R/W PLL0_FBDIV 5:0
116
20
31
42
53
0005 8:0 R/W PLL0_LOCK_CFG 8:0 0-511 0-511
0006 15:0 R/W PLL0_INIT_CFG 15:0 0-65535 0-65535
0007 7:0 R/W PLL0_INIT_CFG 23:16 0-255 0-255
000A 15:0 R/W RSVD_ATTR0 15:0 0-65535 0-65535
000F 1 R/W PLL1_DMON_CFG 0 0-1 0-1
000F 0 R/W PLL0_DMON_CFG 0 0-1 0-1
0011 15:0 R/W COMMON_CFG 15:0 0-65535 0-65535
0012 15:0 R/W COMMON_CFG 31:16 0-65535 0-65535
0013 7:0 R/W PLL_CLKOUT_CFG 7:0 0-255 0-255
0019 15:0 R/W BIAS_CFG 15:0 0-65535 0-65535
Send Feedback

Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English