Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 267
UG482 (v1.9) December 19, 2016
Table D-2 lists the DRP map of the GTPE2_CHANNEL primitive sorted by address.
Note:
The reserved bits should NOT be modified. Attributes that are not described explicitly are set
automatically by the 7 Series FPGAs Transceivers Wizard. These attributes must be left at their
defaults, except for use cases that explicitly request different values.
Table D-2: DRP Map of GTPE2_CHANNEL Primitive
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
0000 15 R/W ACJTAG_RESET 0 0-1 0-1
0000 14 R/W ACJTAG_DEBUG_MODE 0 0-1 0-1
0000 13 R/W ACJTAG_MODE 0 0-1 0-1
0000 1R/W UCODEER_CLR 0 0-1 0-1
000C 15:11 R/W RXBUFRESET_TIME 4:0 0-31 0-31
000D 14:10 R/W RXCDRPHRESET_TIME 4:0 0-31 0-31
000D 9:5 R/W RXCDRFREQRESET_TIME 4:0 0-31 0-31
000D 4:0 R/W RXPMARESET_TIME 4:0 0-31 0-31
000E 11:7 R/W RXPCSRESET_TIME 4:0 0-31 0-31
000E 6:0 R/W RXLPMRESET_TIME 6:0 0-127 0-127
000F 11:7 R/W RXISCANRESET_TIME 4:0 0-31 0-31
0010 15 R/W RXSYNC_OVRD 0 0-1 0-1
0010 14 R/W TXSYNC_OVRD 0 0-1 0-1
0010 13 R/W RXSYNC_SKIP_DA 0 0-1 0-1
0010 12 R/W TXSYNC_SKIP_DA 0 0-1 0-1
0010 11 R/W TXSYNC_MULTILANE 0 0-1 0-1
0010 10 R/W RXSYNC_MULTILANE 0 0-1 0-1
0010 9:5 R/W TXPCSRESET_TIME 4:0 0-31 0-31
0010 4:0 R/W TXPMARESET_TIME 4:0 0-31 0-31
0011 14 R/W RX_XCLK_SEL 0
RXREC 0
RXUSR 1
0011 13:11 R/W RX_DATA_WIDTH 2:0
16 2
20 3
32 4
40 5
0011 10:6 R/W RX_CLK25_DIV 4:0
10
21
32
43
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Xilinx 7 Series Specifications

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Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English