Xilinx 7 Series User Manual

268 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Appendix D: DRP Address Map of the GTP Transceiver
0011
(Cont’d)
10:6 R/W RX_CLK25_DIV 4:0
54
65
76
87
98
10 9
11 10
12 11
13 12
14 13
15 14
16 15
17 16
18 17
19 18
20 19
21 20
22 21
23 22
24 23
25 24
26 25
27 26
28 27
29 28
30 29
31 30
32 31
0011 5:4 R/W RX_CM_SEL 1:0 0-3 0-3
0011 0 R/W RXPRBS_ERR_LOOPBACK 0 0-1 0-1
0012 15:12 R/W SATA_BURST_SEQ_LEN 3:0 0-15 0-15
0012 11:10 R/W OUTREFCLK_SEL_INV 1:0 0-3 0-3
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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Xilinx 7 Series Specifications

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Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English